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Final Electrical Specifications
LT1943 High Current Quad Output Regulator for TFT LCD Panels
FEATURES
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DESCRIPTIO
September 2003
s s s s s s s s
4 Integrated Switches: 2.4A Buck, 2.6A Boost, 0.35A Boost, 0.35A Inverter (Guaranteed Minimum Current Limit) Fixed Frequency, Low Noise Outputs Soft Start for all Outputs Externally Programmable VON Delay Integrated Schottky Diode for VON Output PGOOD Pin for AVDD Output Disconnect 4.5V to 22V Input Voltage Range PanelProtectTM Circuitry Disables VON Upon Fault Thermally Enhanced 28-Lead TSSOP
APPLICATIO S
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Large TFT-LCD Desktop Monitor Displays Flat Panel Televisions
The LT(R)1943 quad output adjustable switching regulator provides power for large TFT LCD panels. The device, housed in a low profile 28 pin thermally enhanced TSSOP package, can generate a 3.3V or 5V logic supply along with the triple output supply required for the TFT LCD panel. Operating from an input range of 4.5V to 22V, a step-down regulator provides a low voltage output VLOGIC with up to 2A current. A high-power step-up converter, a lowerpower step-up converter and an inverting converter provide the three independent output voltages AVDD, VON and VOFF required by the LCD panel. A high-side PNP provides delayed turn-on of the VON signal and can handle up to 30mA. Protection circuitry ensures VON is disabled if any of the four outputs are more than 10% below normal voltage. All switchers are synchronized to the internal 1.2MHz clock, allowing the use of low profile inductors and ceramic capacitors throughout. A current mode architecture provides excellent transient response. For best flexibility, all outputs are adjustable. Soft-start is included in all four channels. A PGOOD pin can drive an optional PMOS pass device to provide output disconnect for the AVDD output.
, LTC and LT are registered trademarks of Linear Technology Corporation. PannelProtect is a trademark of Linear Technology Corporation.
TYPICAL APPLICATIO
VOFF -10V 50mA 2.2F ZHCS400 VIN, 8V TO 20V 0.47F 16V 80.6k ZHCS400 SW4 NFB4 10.0k 10pF 10H FB4 BIAS BOOST CMDSH-3 16.2k 0.22F 10V SW1 VIN 10F
10H 1F 25V
B240A
AVDD 13V 500mA 95.3k 10F
33H
10H
SW3
SW2 FB2 RUN-SS SS-234 CT PGOOD VON E3 232k FB3 PGOOD 0.015F 0.015F 0.047F
10.0k
LT1943
VON 30V 30mA
RUN-SS 2V/DIV VLOGIC 5V/DIV AVDD 10V/DIV VOFF 10V/DIV VE3 20V/DIV VON 50V/DIV IIN(AVG) 1A/DIV 5ms/DIV
VLOGIC 3.3V 2A
4.7H B230A
FB1 10.0k 22F 27.4k 100pF 2.2nF 6.81k VC1 VC2 VC3
GND SGND VC4
10.0k 2.2F
100pF 2.2nF
47.5k 100pF 680pF
13k 100pF 2.2nF
0.47F
Figure 1. Quad Output TFT-LCD Power Supply
1943 F01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Startup Waveforms
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LT1943
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GND VC1 VC2 FB1 FB2 FB3 NFB4 FB4 VC3 1 2 3 4 5 6 7 8 9 29 28 SW2 27 SW2 26 VON 25 CT 24 E3 23 PGOOD 22 BIAS 21 SW3 20 GND 19 SW4 18 RUN-SS 17 SS-234 16 VIN 15 VIN
VIN Voltage .............................................................. 25V BOOST Voltage ........................................................ 36V BOOST Voltage Above SW1 ..................................... 25V BIAS Pin Voltage ..................................................... 18V SW2, SW4 Pin Voltages .......................................... 40V SW3 Voltage ............................................................ 36V FB1, FB2, FB3, FB4 Voltages ...................................... 4V NFB4 Voltage ................................................ +6V, -0.6V VC1, VC2, VC3, VC4 Pin Voltages .............................. 6V RUN-SS, SS-234 Pin Voltages ................................... 6V PGOOD Pin Voltage ................................................. 36V E3 Pin Voltage ......................................................... 36V VON Voltage ............................................................. 36V CT Pin Voltage ........................................................... 6V Junction Temperature ........................................... 125C Operating Temperature Range (Note 2) ...-40C to 85C Storage Temperature Range ..................-65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT1943EFE
VC4 10 SGND 11 BOOST 12 SW1 13 SW1 14
FE PART MARKING 1943EFE
FE PACKAGE 28-LEAD PLASTIC TSSOP EXPOSED PAD (PIN 29) IS GROUND (MUST BE SOLDERED TO PCB)
TJMAX = 150C, JA = 25C/W, JC = 7.5C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, RUN-SS, SS-234 = 2.5V unless otherwise noted.
PARAMETER Minimum Input Voltage Maximum Input Voltage Quiescent Current RUN-SS, SS-234 Pin Current RUN-SS, SS-234 Threshold BIAS Pin Voltage to Begin SS-234 Charge BIAS Pin Current FB Threshold Offset to Begin CT Charge CT Pin Current Source CT Threshold to Power VON VON Switch Drop Maximum VON Current PGOOD Threshold Offset PGOOD Pin Leakage Master Oscillator Frequency
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ELECTRICAL CHARACTERISTICS
CONDITIONS
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MIN
TYP
MAX 4.5 22
UNITS V V mA A A V
Not Switching RUN-SS = SS-234 = 0V RUN-SS, SS-234 = 0.4V 2.4 90 16 1.0
q
10 35 1.7 0.8 2.8 10.5 125 20 1.1 180 30 90 60 125 1.2 250 0.5
14 45
3.15 15 160 25 1.2 240 160 1 1.35 1.46
BIAS = 3.1V, All Switches Off (Note 3) All FB Pins = 1.5V All FB Pins = 1.5V VON Current = 30mA VE3 = 30V VPGOOD = 36V 1.1 1.0
Foldback Switching Frequency Frequency Shift Threshold on FB
All FB Pins = 0V 200kHz
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V mA mV A V mV mA mV A MHz MHz kHz V
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LT1943
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, RUN-SS, SS-234 = 2.5V unless otherwise noted.
PARAMETER SWITCH 1 (2.4A BUCK) FB1 Voltage
q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 1.23 1.22
TYP 1.25 0.01
MAX 1.27 1.27 0.03 600
UNITS V V %/V nA V/V mhos
FB1 Voltage Line Regulation FB1 Pin Bias Current Error Amplifier 1 Voltage Gain Error Amplifier 1 Transconductance Switch 1 Current Limit Switch 1 VCESAT Switch 1 Leakage Current Minimum BOOST Voltage Above SW1 Pin BOOST Pin Current Maximum Duty Cycle (SW1) SWITCH 2 (2.6A BOOST) FB2 Voltage
4.5V < VIN < 22V (Note 4) I = 5A Duty Cycle = 35% ISW = 2A FB1 = 1.5V ISW = 1.5A ISW = 1.5A
q q q
100 200 450 2.4 3.2 310 0.1 1.8 30 82 1.23 1.22 92 1.25 0.01
4.3 470 10 2.5 50
A mV A V mA %
q
1.27 1.27 0.03 1000
V V %/V nA V/V mhos
FB2 Voltage Line Regulation FB2 Pin Bias Current Error Amplifier 2 Voltage Gain Error Amplifier 2 Transconductance Switch 2 Current Limit Switch 2 VCESAT Switch 2 Leakage Current BIAS Pin Current Maximum Duty Cycle (SW2) SWITCH 3 (350mA BOOST) FB3 Voltage
4.5V < VIN < 22V (Note 4) I = 5A
q q
220 200 450 2.6 3.8 360 0.1 45
4.9 540 1
A mV A mA %
ISW2 = 2A FB2 = 1.5V ISW2 = 2A
q
85 1.23 1.22
92 1.25 0.01 1.27 1.27 0.03 600
q
V V %/V nA V/V mhos
FB3 Voltage Line Regulation FB3 Pin Bias Current Error Amplifier 3 Voltage Gain Error Amplifier 3 Transconductance Switch 3 Current Limit Switch 3 VCESAT Switch 3 Leakage Current BIAS Pin Current Maximum Duty Cycle (SW3)
4.5V < VIN < 22V (Note 4) I = 5A
q q
100 200 450 0.35 0.5 180 0.1 14 84 83 88 700
0.7 280 1
A mV A mA % % mV
ISW3 = 0.2A FB3 = 1.5V ISW3 = 0.2A
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Schottky Diode Drop
I = 170mA
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LT1943
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. RUN-SS, SS-234 = 2.5V unless otherwise noted.
PARAMETER SWITCH 4 (350mA INVERTER) FB4 Voltage
q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 1.23 1.22
TYP 1.25 0.01
MAX 1.27 1.27 0.03 600 1.275 1.275 0.03 600
UNITS V V %/V nA V V %/V nA V/V mhos
FB4 Voltage Line Regulation FB4 Pin Bias Current NFB4 Voltage (VFB4-VNFB4)
4.5V < VIN < 22V (Note 4)
q q
100 1.215 1.205 1.245 0.01 100 200 450
NFB4 Voltage Line Regulation NFB4 Pin Bias Current Error Amplifier 4 Voltage Gain Error Amplifier 4 Transconductance Switch 4 Current Limit Switch 4 VCESAT Switch 4 Leakage Current BIAS Pin Current due to SW4 Maximum Duty Cycle (SW4)
4.5V < VIN < 22V (Note 5) I = 5A
q
0.35
0.5 260 0.1 15
0.7 390 1
A mV A mA % %
ISW4 = 0.3A ISW4 = 0.3A
q
84 83
88
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1943E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization, and correlation with statistical process controls.
Note 3: The CT pin is held low until FB1, FB2, FB3 and FB4 all ramp above the FB threshold offset. Note 4: Current flows into FB1, FB2, FB3 and FB4 pins. Note 5: Current flows out of NFB4 pin.
TYPICAL PERFOR A CE CHARACTERISTICS
Maximum Output Current for VLOGIC
2.8 5 TA = 25C 2.6 4 2.4 4.0 L1 = 4.7H 2.2 L1 = 3.3H 2.0 1.8 1.6 1.4 1.2 0 0 5 10 INPUT VOLTAGE (V)
1943 G01
VLOGIC MAXIMUM OUTPUT CURRENT (A)
SW1 CURRENT (A)
3
SW1 CURRENT (A)
80 100
1943 G02
15
4
UW
20
SW1 Current Limit vs Duty Cycle
4.5 TA = 25C
SW1 Current Limit
TYPICAL
3.5
2 MINIMUM 1
3.0
0
20
40 60 DUTY CYCLE (%)
2.5 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
1943 G03
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LT1943 TYPICAL PERFOR A CE CHARACTERISTICS
MINIMUM Input Voltage to Start, VOUT = 3.3V
6.0 TA = 25C 5.5 100 TA = 25C
BOOST PIN CURRENT (mA)
INPUT VOLTAGE (V)
5.0 4.5 4.0 3.5 3.0 0
SW2 CURRENT (A)
0 1.0 1.5 2.0 SW1 CURRENT (A) 2.5 3.0
1943 G05
20
40 60 80 LOAD CURRENT (mA)
SW3 Current Limit
0.8 0.7 0.8 0.7
SW1 VOLTAGE DROP (mV)
SW3 CURRENT (A)
SW4 CURRENT (A)
0.6 0.5 0.4 0.3 0.2 -50 -25
50 25 75 0 TEMPERATURE (C)
SW2 VCESAT
600 TA = 25C 500 500
SW3 VOLTAGE DROP (mV)
SW2 VOLTAGE DROP (mV)
400 300 200 100 0
SW4 VOLTAGE DROP (mV)
0
0.5
1.0 1.5 2.0 SW2 CURRENT (A)
UW
1943 G04
BOOST Pin Current
5.0
SW2 Current Limit
80
4.5
60
4.0
40
3.5
20
3.0
0 100 0.5
2.5 -50
-25
50 0 75 25 TEMPERATURE (C)
100
125
1943 G06
SW4 Current Limit
600
SW1 VCESAT
TA = 25C 500 400 300 200 100 0
0.6 0.5 0.4 0.3 0.2 -50 -25
100
125
50 25 75 0 TEMPERATURE (C)
100
125
0
0.5
1.0 1.5 2.0 SW1 CURRENT (A)
2.5
3.0
1943 G09
1943 G07
1943 G08
SW3 VCESAT
500 TA = 25C 400 400
SW4 VCESAT
TA = 25C
300
300
200
200
100
100
0 2.5 3.0
1943 G10
0
0.1
0.2 SW3 CURRENT (A)
0.3
0 0.4
1943 G11
0
0.1
0.2 SW4 CURRENT (A)
0.3
0.4
1943 G12
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LT1943 TYPICAL PERFOR A CE CHARACTERISTICS
VON Current Limit
100 TA = 25C 1.3 90 1.4
VON CURRENT (mA)
70 60 50 40 30 5 10 15 25 20 VON (V) 30 35 40
FREQUENCY (MHz)
80
SWITCHING FREQUENCY (MHz)
Reference Voltage
1.27 100
REFERENCE VOLTAGE (V)
1.25
BIAS PIN CURRENT (mA)
1.26
1.24
1.23
1.22 -50 -25
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UW
1943 G13
Oscillator Frequency
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -25 0 25 50 75 TEMPERATURE (C) 100 125
1943 G14
Frequency Foldback
TA = 25C
1.2
1.1
1.0 -50
0
0.2
0.4 0.6 0.8 1.0 FEEDBACK VOLTAGE (V)
1.2
1943 G14
Bias Pin Current
80
60 ISW2 = 1.5A ISW3 = 0.2A ISW4 = 0.3A
40
20 ISW2 = ISW3 = ISW4 = 0A 0 50 -50 -25 25 75 0 TEMPERATURE (C)
50 25 75 0 TEMPERATURE (C)
100
125
100
125
1943 G16
1943 G17
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LT1943
PI FU CTIO S
GND (Pins 1, 20, Exposed Pad Pin 29): Ground. Tie both GND pins and the exposed pad directly to local ground plane. The ground metal to the exposed pad should be as wide as possible for better heat dissipation. Multiple vias (to ground plane under the ground backplane) placed close to the exposed pad can further aid in reducing thermal resistance. VC1 (Pin 2): Switching Regulator 1 Error Amplifier Compensation. Connect a resistor/capacitor network in series with this pin. VC2 (Pin 3): Error Amplifier Compensation for Switcher 2. Connect a resistor/capacitor network in series with this pin. FB1 (Pin 4): Switching Regulator 1 Feedback. Tie the resistor divider tap to this pin and set VLOGIC according to VLOGIC = 1.25 * (1 + R2/R1). Reference designators refer to Figure 2. FB2 (Pin 5): Feedback for Switch 2. Tie the resistor divider tap to this pin and set AVDD according to AVDD = 1.25 * (1 + R6/R5). FB3 (Pin 6): Switching Regulator 3 Feedback. Tie the resistor divider tap to this pin and set VON according to VON = 1.25 * (1 + R9/R8) - 150mV. NFB4 (Pin 7): Switching Regulator 4 Negative Feedback. Switcher 4 can be used to generate a positive or negative output. When regulating a negative output, tie the resistor divider tap to this pin. Negative output voltage can be set by the equation VOFF = -1.25 * (R3/R4) with R4 set to 10k. Tie the NFB4 pin to FB4 for positive output voltages. FB4 (Pin 8): Feedback for Switch 4. When generating a positive voltage from switch 4, tie the resistor divider tap to this pin. When generating a negative voltage, tie a 10k resistor between FB4 and NFB4 (R4). VC3 (Pin 9): Switching Regulator 3 Error Amplifier Compensation. Connect a resistor/capacitor network in series with this pin. VC4 (Pin 10): Switching Regulator 4 Error Amplifier Compensation. Connect a resistor/capacitor network in series with this pin. SGND (Pin 11): Signal Ground. Return ground trace from the FB resistor networks and VC pin compensation components directly to this pin and then tie to ground. BOOST (Pin 12): The BOOST pin is used to provide a drive voltage, higher than VIN, to the switch 1 drive circuit. SW1 (Pins 13, 14): The SW1 pins are the emitter of the internal NPN bipolar power transistor for switching regulator 1. These pins must be tied together for proper operation. Connect these pins to the inductor, catch diode and boost capacitor. VIN (Pins 15, 16): The VIN pins supply current to the LT1943's internal regulator and to the internal power transistor for switch 1. These pins must be tied together and locally bypassed. SS-234 (Pin 17): This is the soft-start pin for switching regulators 2, 3 and 4. Place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. When the BIAS pin reaches 2.8V, a 1.7A current source begins charging the capacitor. When the capacitor voltage reaches 0.8V, switches 2, 3 and 4 turn on and begin switching. For slower start-up, use a larger capacitor. When this pin is pulled to ground, switches 2, 3 and 4 are disabled. For complete shutdown, tie RUN-SS to ground. RUN-SS (Pin 18): This is the soft-start pin for switching regulator 1. Place a soft-start capacitor here to limit startup inrush current and output voltage ramp rate. When power is applied to the VIN pin, a 1.7A current source charges the capacitor. When the voltage at this pin reaches 0.8V, switch 1 turns on and begins switching. For slower start-up, use a larger capacitor. For complete shutdown, tie RUN-SS to ground. SW4 (Pin 19): This is the collector of the internal NPN bipolar power transistor for switching regulator 4. Minimize metal trace area at this pin to keep EMI down.
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LT1943
PI FU CTIO S
SW3 (Pin 21): This is the collector of the internal NPN bipolar power transistor for switching regulator 3. Minimize metal trace area at this pin to keep EMI down. BIAS (Pin 22): The BIAS pin is used to improve efficiency when operating at higher input voltages. Connecting this pin to the output of switching regulator 1 forces most of the internal circuitry to draw its operating current from VLOGIC rather than VIN. Switches 2, 3 and 4 drivers are supplied by BIAS and will not switch until this pin reaches approximately 2.8V. BIAS must be tied to VLOGIC. PGOOD (Pin 23): Power Good Comparator Output. This is the open collector output of the power good comparator and can be used in conjunction with an external P-Channel MOSFET to provide output disconnect for AVDD. When switcher 2's output reaches approximately 90% of its programmed voltage, PGOOD will be pulled to ground. This will pull down on the gate of the MOSFET, connecting AVDD. A 100k pull-up resistor between the source and drain of the P-channel MOSFET keeps it off when switcher 2's output is low. E3 (Pin 24): This is switching regulator 3's output and the emitter of the output disconnect PNP. Tie the output capacitor and resistor divider here. CT (Pin 25): Timing Capacitor Pin. This is the input to the VON timer and programs the time delay from all four feedback pins reaching 1.125V to VON turning on. The CT capacitor value can be set using the equation C = (20A * tDELAY)/1.1V. VON (Pin 26): This is the delayed output for switching regulator 3. VON reaches its programmed voltage after the internal CT timer times out. Protection circuitry ensures VON is disabled if any of the four outputs are more than 10% below normal voltage. SW2 (Pins 27, 28): The SW2 pins are the collector of the internal NPN bipolar power transistor for switching regulator 2. These pins must be tied together. Minimize trace area at these pins to keep EMI down.
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LT1943
BLOCK DIAGRA
VIN C1 VIN 15 16
VLOGIC R2 4 R1 AVDD R14 PGOOD 23 FB1
MASTER OSCILLATOR 1.2MHz
R6 5 R5
FB2
20A CT 25 C9
1.125V
VIN 1.7A RUN-SS 18 C5 INTERNAL REGULATOR AND REFERENCE
SS-234 17 C4
1.7A
SW2 SW3 SW4 LOCKOUT FOLDBACK OSCILLATOR
- +
R9 VE3 R8 6 FB3
VON VON C15 26
W
FOLDBACK OSCILLATOR
SLOPE COMPENSATION
BOOST 12
D2
-
DRIVER 3A SWITCH 13 R SQ SW1 14 D1
C3 L1
VLOGIC
+
C2
- +
1.25V 1.25V
-
gm
VC1 10 C20 VC2
R10 C11 R11
+
3
-
gm
C21
C12
- +
R SQ DRIVER 2.6A SWITCH
+ - - - - +
FOLDBACK OSCILLATOR 1.25V
BIAS 22 27
SW2 28 C16 D5
L2 VIN
L3
AVDD C8
SLOPE COMPENSATION
FB4 8 NFB4 C24 7 VC4 10 C23
R4
- + -
gm
R3 R13 C14
- +
SW4 19 R SQ DRIVER 400mA SWITCH C7 L4 VLOGIC D6 VOFF D3 C6
+
1.25V
BIAS
SLOPE COMPENSATION
VC3 R12 C22 C13
2.8V
-
gm
9
- +
SW3 20 R SQ DRIVER 300mA SWITCH L5 VIN
+
1.25V
-
FOLDBACK OSCILLATOR
+
1.1V
SLOPE COMPENSATION
E3 24 C10
VE3
Figure 2.
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LT1943
OPERATIO
The LT1943 is a highly integrated power supply IC containing four separate switching regulators. All four switchers have their own oscillator with frequency foldback and use current mode control. Switching regulator 1 consists of a step-down regulator with a current limit of 2.4A. Switching regulator 2 is a boost regulator with a current limit of 2.6A and switchers 3 and 4 are 0.35A boost regulators. Switching regulator 4 has two feedback pins (FB4 and NFB4) and can directly regulate positive or negative output voltages. When power is applied to VIN, the RUN-SS pin starts charging and when its voltage reaches 0.8V, switcher 1 is enabled. (See Figure 2) The RUN-SS pin is used for softstart and limits the ramp-rate for VLOGIC. Using a larger capacitor at the RUN-SS pin will cause VLOGIC to start more slowly. Switching regulators 2, 3 and 4 are driven by the BIAS pin which must be connected to VLOGIC. VLOGIC is the first to come up and when it reaches 2.8V, the SS234 pin will begin charging to enable switches 2, 3 and 4. AVDD and VOFF will then begin rising and their ramp rate is determined by the capacitor tied to the SS-234 pin. When AVDD reaches approximately 90% of its programmed voltage, the PGOOD pin will be pulled low. When all outputs reach 90% of their programmed voltages, the CT timer will trigger and a 20A current source begins to charge the CT pin. When the CT pin reaches 1.1V, the output disconnect PNP turns on, connecting VON. In the event of any of the 4 outputs dropping below 10% of its normal voltage, PanelProtect circuitry pulls the CT pin to ground, disabling VON. When needed, the PGOOD pin can be used to drive the gate of a P-channel MOSFET that functions as output disconnect for AVDD. For complete shutdown, the RUN-SS pin must be pulled to ground.
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RUN-SS 2V/DIV VLOGIC 5V/DIV IL1 1A/DIV SS-234 2V/DIV AVDD 20V/DIV IL2+L3 1A/DIV PGOOD 20V/DIV 5ms/DIV
1943 F03a
(3a)
VOFF 10V/DIV IL4 500mA/DIV VE3 20V/DIV IL5 500mA/DIV VCT 2V/DIV VON 50V/DIV 5ms/DIV
1943 F03b
(3b) Figure 3. LT1943 Power-Up Sequence. (Traces From Both Photos are Synchronized to the Same Trigger)
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LT1943
PACKAGE DESCRIPTIO U
FE Package 28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation EB
4.75 (.187) 9.60 - 9.80* (.378 - .386) 4.75 (.187) 28 2726 25 24 23 22 21 20 19 18 1716 15 6.60 0.10 4.50 0.10 SEE NOTE 4 0.45 0.05
2.74 (.108)
EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE
2.74 6.40 (.108) BSC
1.05 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.20 (.047) MAX 0 - 8
4.30 - 4.50* (.169 - .177)
0.09 - 0.20 (.0036 - .0079)
0.45 - 0.75 (.018 - .030)
0.65 (.0256) BSC
0.195 - 0.30 (.0077 - .0118)
0.05 - 0.15 (.002 - .006)
FE28 (EB) TSSOP 0203
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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LT1943
TYPICAL APPLICATIO
VOFF -10V 50mA 2.2F
ZHCS400
80.6k ZHCS400 0.47F
10.0k
10pF FB4 BIAS BOOST CMDSH-3 0.22F 4.7H B230A SW1
VLOGIC 3.3V 1.5A
16.2k
10.0k 22F 27.4k 100pF 2.2nF
RELATED PARTS
PART NUMBER LT1615/LT1615-1 LT1940 LT1944/LT1944-1 LT1945 LT1946/LT1946A LT1947 LT3464 DESCRIPTION 300mA/80mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC Converters Dual Output 1.4A (IOUT), Constant 1.1MHz, High Efficiency Step-Down DC/DC Converter Dual Output 350mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC Converter Dual Output, Pos/Neg, 350mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC Converter 1.5mA (ISW), 1.2MHz/2.7MHz, High Efficiency Step-Up DC/DC Converter 1.1A, 3MHz, TFT-LCD Triple Output Switching Regulator COMMENTS VIN: 1.2V to 15V, VOUT(MAX): 34V, IQ: 20A, ISD: <1A, ThinSOTTM Package VIN: 3V to 25V, VOUT(MIN): 1.2V, IQ: 2.5mA, ISD: <1A, TSSOP-16E Package VIN: 1.2V to 15V, VOUT(MAX): 34V, IQ: 20A, ISD: <1A, MS Package VIN: 1.2V to 15V, VOUT(MAX): 34V, IQ: 20A, ISD: <1A, MS Package VIN: 2.75V to 16V, VOUT(MAX): 34V, IQ: 20A, ISD: <1A, MS Package VIN: 2.7V to 8V, VOUT(MAX): 34V, IQ: 9.5mA, ISD: <1A, MS Package
85mA (ISW), Constant Off-Time, High Efficiency Step-Up DC/DC VIN: 2.3V to 10V, VOUT(MAX): 34V, IQ: 25A, ISD: <0.5A, Converter with Integrated Schottky and Output Disconnect PNP ThinSOT Package
ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507 q www.linear.com
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5V Input, Quad Output TFT-LCD Power Supply
VIN 4.5V TO 8V 10H 10F 33H 10F 95.3k SW4 NFB4 LT1943 VIN SW3 SW2 FB2 RUN-SS SS-234 CT PGOOD VON E3 232k FB3 FB1 VC1 VC2 VC3 GND SGND VC4 10.0k 2.2F 0.015F 0.015F 0.047F AVDD 13V 500mA VON 30V 30mA 10.0k FDN360P 100k 4.7H B240A 6.81k 100pF 4700pF 30.1k 100pF 1500pF 13k 100pF 2.2nF 0.47F
1943 F01
1943i LT/TP 0903 1K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2003

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